Altera Arria 10 Avalon-MM DMA - Manual (Page 14)

Getting Started with the Avalon-MM DMA
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2015.05.14
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You can download this Qsys design example, ep_g3x8_avmm256_integrated.qsys, from the
<install_dir>/
ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/example_design/a10 directory.
The design example includes the following components:
Avalon-MM DMA for PCI Express
This IP core includes highly efficient DMA Read and DMA Write modules. The DMA Read and Write
modules effectively move large blocks of data between the PCI Express address domain and the Avalon-
MM address domain using burst data transfers. Depending on the configuration you select, the DMA
Read and DMA Write modules use either a 128- or 256-bit Avalon-MM datapath.
In addition to high performance data transfer, the DMA Read and DMA Write modules ensure that the
requests on the PCI link adhere to the PCI Express Base Specification, 3.0. The DMA Read and Write
engines also perform the following functions:
• Divide the original request into multiple requests to avoid crossing 4KByte boundaries.
• Divide the original request into multiple requests to ensure that the maximum payload size is equal to
or smaller than the maximum payload size for write requests and maximum read request size for read
requests.
• Supports out-of-order completions when the original request is divided into multiple requests to
adhere to the read request size.
Using the DMA Read and DMA Write modules, you can specify descriptor entry table entries with large
payloads.
On-Chip Memory IP core
This IP core stores the DMA data. This 32-KByte memory has a 256-bit data width.
Descriptor Controller
The Descriptor Controller manages the Read DMA and Write DMA modules. Host software programs
the Descriptor Controller internal registers with the location of the descriptor table. The Descriptor
Controller instructs the Read DMA module to copy the entire table to its internal FIFO. It then pushes the
table entries to DMA Read or DMA Write modules to transfer data. The Descriptor Controller also sends
DMA status upstream via an Avalon-MM TX slave port.
In this example design the Descriptor Controller parameter, Instantiate internal descriptor controller, is
on. Consequently, the Descriptor Controller is integrated into the Avalon-MM bridge as shown in the
figure below. Embedding the Descriptor Controller in Avalon-MM bridge simplifies the design. If you
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