Altera Arria 10 Avalon-MM DMA - Manual (Page 129)

Date Version Changes Made
• Added the following optimizations for the Descriptor Controller:
• Optimized performance for smaller payloads such as 64-byte
Ethernet packets
• Reduced overhead for host updates
• Support for concurrent dynamic host updates and DMA
operation
• Support for choice to embed Descriptor Controller in the
Avalon-MM bridge or instantiate separately
• Added access to selected Configuration Space registers and link
status registers through the optional Control Register Access
(CRA) Avalon-MM slave port.
• Added simulation support for Phase 2 and Phase 3 equalization
when requested by third-party BFM for Gen3 variants.
• Added multiple MSI/MSI-X support.
Made the following changes to the user guide:
• Removed 125 MHz clock as optional
refclk
frequency in Arria 10
devices. Arria 10 devices support an 100 MHz reference clock as
specified by the PCI Express Base Specification, Rev 3.0
• Corrected values for Maximum payload size parameter. The sizes
available are 128 or 256 bytes.
• Enhanced definition of Device ID and Sub-system Vendor ID to
say that these registers are only valid in the Type 0 (Endpoint)
Configuration Space.
• Removed 125 MHz clock as optional
refclk
frequency in Arria 10
devices. Arria 10 devices support an 100 MHz reference clock as
specified by the PCI Express Base Specification, Rev 3.0.
• Added Next Steps in Creating a Design for PCI Express to
Datasheet chapter.
• Removed the Transaction Layer Protocol Details chapter. This
information only applies to the Avalon-ST interface.
• Removed
txdatavalid0
signal from the PIPE interface. This
signal is not available.
• Removed references to the MegaWizard ® Plug-In Manager. In
14.0 the IP Parameter Editor Powered by Qsys has replaced the
MegaWizard Plug-In Manager.
• Added definitions for
test_in[2]
,
test_in[6]
and
test_in[7]
.
• Corrected interface widths in the Performance and Resource
Utilization Arria 10 Avalon-MM DMA for PCI Express table in the
Datasheet: Arria 10 Avalon-MM DMA for PCIe chapter.
• Removed discussion of
pclk
. This clock is not customer accessible
in Arria 10 devices.
UG-01145_avmm_dma
2015.05.14
Revision History for the Avalon-MM Interface with DMA B-3
Additional Information Altera Corporation
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