Altera Arria 10 Avalon-MM DMA - Manual (Page 29)

Related Information
PCI Express Base Specification 2.1 or 3.0
PCI Express and PCI Capabilities Parameters
This group of parameters defines various capability properties of the IP core. Some of these parameters
are stored in the PCI Configuration Space - PCI Compatible Configuration Space. The byte offset
indicates the parameter address.
Device Capabilities
Table 3-5: Capabilities Registers
Parameter Possible Values Default Value Description
Maximum
payload size
128 bytes
256 bytes
512 bytes
1024 bytes
2048 bytes
128 bytes Specifies the maximum payload size supported. This
parameter sets the read-only value of the max payload
size supported field of the Device Capabilities register
(0x084[2:0]). Address: 0x084.
The Maximum payload size is 256 Bytes for the
Avalon-MM interface and for the Avalon-MM with
DMA interface.
Completion
timeout
range
ABCD
BCD
ABC
AB
B
A
None
ABCD Indicates device function support for the optional
completion timeout programmability mechanism. This
mechanism allows system software to modify the
completion timeout value. This field is applicable only to
Root Ports and Endpoints that issue requests on their
own behalf. This parameter must be set to NONE for the
Avalon-MM with DMA interface. Completion timeouts
are specified and enabled in the Device Control 2
register (0x0A8) of the PCI Express Capability Structure
Version. For all other functions this field is reserved and
must be hardwired to 0x0000b. Four time value ranges
are defined:
• Range A: 50 us to 10 ms
• Range B: 10 ms to 250 ms
• Range C: 250 ms to 4 s
• Range D: 4 s to 64 s
UG-01145_avmm_dma
2015.05.14
PCI Express and PCI Capabilities Parameters 3-9
Parameter Settings Altera Corporation
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