Contents
Datasheet............................................................................................................. 1-1
Arria 10 Avalon-MM DMA Interface for PCIe Datasheet.....................................................................1-1
Features ........................................................................................................................................................ 1-2
Release Information ....................................................................................................................................1-6
Device Family Support ...............................................................................................................................1-7
Example Designs..........................................................................................................................................1-7
Debug Features ............................................................................................................................................1-7
IP Core Verification ....................................................................................................................................1-7
Compatibility Testing Environment ............................................................................................ 1-8
Performance and Resource Utilization ....................................................................................................1-8
Recommended Speed Grades ....................................................................................................................1-8
Steps in Creating a Design for PCI Express............................................................................................. 1-9
Getting Started with the Avalon-MM DMA ...................................................... 2-1
Generating the Testbench ..........................................................................................................................2-2
Understanding the Simulation Generated Files ......................................................................... 2-4
Understanding Simulation Log File Generation......................................................................... 2-4
Simulating the Example Design in ModelSim......................................................................................... 2-4
Running a Gate-Level Simulation..............................................................................................................2-5
Generating Quartus II Synthesis Files.......................................................................................................2-5
Creating a Quartus II Project .................................................................................................................... 2-5
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)................................................. 2-6
Compiling the Design .................................................................................................................................2-6
Descriptor Controller Connectivity when Instantiated Separately.......................................................2-7
Parameter Settings.............................................................................................. 3-1
System Settings.............................................................................................................................................3-1
Interface System Settings ........................................................................................................................... 3-5
Base Address Register (BAR) Settings ......................................................................................................3-7
Device Identification Registers ..................................................................................................................3-8
PCI Express and PCI Capabilities Parameters ........................................................................................3-9
Device Capabilities ..........................................................................................................................3-9
Error Reporting .............................................................................................................................3-10
Link Capabilities ........................................................................................................................... 3-11
MSI and MSI-X Capabilities ........................................................................................................3-11
Power Management ......................................................................................................................3-12
PCIe Address Space Settings.................................................................................................................... 3-13
Physical Layout of Hard IP In Arria 10 Devices.................................................4-1
Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates..............................................4-4
TOC-2
Altera Corporation
