Altera Arria 10 Avalon-MM DMA User Manual
Page 64
Table 5-22: PIPE Interface Signals
In the following table, signals that include lane number 0 also exist for lanes 1-7. These signals are for simulation
only. For Quartus II software compilation, these pipe signals can be left floating. In Qsys, the signals that are part
of the PIPE interface have the prefix, hip_pipe. The signals which are included to simulate the PIPE interface have
the prefix, hip_pipe_sim_pipe
Signal
Direction
Description
currentcoeff0[17:0]
Output
For Gen3, indicates the coefficients to be used by the transmitter.
The 18 bits specify the following coefficients:
• [5:0]: C-1
• [11:6]: C0
• [17:12]: C+1
currentrxpreset0[2:0]
Output
For Gen3 designs, specifies the current preset.
eidleinfersel0[2:0]
Output
Electrical idle entry inference mechanism selection. The
following encodings are defined:
• 3'b0xx: Electrical Idle Inference not required in current
LTSSM state
• 3'b100: Absence of COM/SKP Ordered Set the in 128 us
window for Gen1 or Gen2
• 3'b101: Absence of TS1/TS2 Ordered Set in a 1280 UI interval
for Gen1 or Gen2
• 3'b110: Absence of Electrical Idle Exit in 2000 UI interval for
Gen1 and 16000 UI interval for Gen2
• 3'b111: Absence of Electrical idle exit in 128 us window for
Gen1
phystatus0
Input
PHY status <n>. This signal communicates completion of several
PHY requests.
powerdown0[1:0]
Output
Power down <n>. This signal requests the PHY to change its
power state to the specified state (P0, P0s, P1, or P2).
rate[1:0]
Output
Controls the link signaling rate. The following encodings are
defined:
• 2'b00: Gen1
• 2'b01: Gen2
• 2'b10: Gen3
• 2'b11: Reserved
rxblkst0
Input
For Gen3 operation, indicates the start of a block in the receive
direction.
rxdata0[31:0]
Input
Receive data. This bus receives data on lane <n>.
UG-01145_avmm_dma
2015.05.14
PIPE Interface Signals
5-23
IP Core Interfaces
Altera Corporation