Altera Arria 10 Avalon-MM DMA - Manual (Page 84)

Bits Register Description Reset Value Access
[5] When set, indicates a configuration error has been detected in
CvP mode which is reported as correctable. This bit is set
whenever a
CVP_CONFIG_ERROR
occurs while in
CVP_MODE
.
0 RW1CS
[4:2] Reserved. 0 RO
[1] When set, the retry buffer correctable ECC error status indicates
an error.
0 RW1CS
[0] When set, the RX buffer correctable ECC error status indicates an
error.
0 RW1CS
Related Information
PCI Express Base Specification 3.0
DMA Descriptor Controller Registers
The DMA Descriptor Controller manages Read and Write DMA operations. The Descriptor Controller
supports up to 128 descriptors for read and write DMAs. Host software running on an embedded CPU
programs the Descriptor Controller internal registers with the location and size of the descriptor table
residing in the PCI Express main memory. The DMA Descriptor Controller instructs the Read DMA to
copy the table to its own internal FIFO. When the DMA Descriptor Controller is instantiated as a separate
component, it drives table entries on the
RdDmaRxData_i[159:0]
and
WrDmaRxData_i[159:0]
buses.
When the DMA Descriptor Controller is embedded in the Avalon-MM bridge, it drives this information
on an internal conduit interface.
Figure 6-8: Block Diagram for Internal Descriptor Controller
PCIe Avalon-MM Bridge
Hard IP for PCIe Using Avalon-MM Interface
Altera FPGA
Qsys System
with Internal Descriptor Controller
Memory
Read DMA
Write DMA
Hard IP
for PCIe
RX Master
TX Slave
DMA
Descriptor
Controller
Avalon-MM Burst
Master 256 Bits
Avalon-MM Burst
Master 256 Bits
Avalon-MM Master
Avalon-MM Slave Single DWORD
Avalon-ST Control/Status Avalon-ST
256 Bits
FIFO
Internal Conduit
UG-01145_avmm_dma
2015.05.14
DMA Descriptor Controller Registers 6-15
Registers Altera Corporation
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