Altera Arria 10 Avalon-MM DMA User Manual
Page 51
Avalon-ST Descriptor Status Interface when Instantiated Separately
When DMA module completes the processing for one Descriptor Instruction, it returns DMA Status to
the Descriptor Controller via the following interfaces.
Table 5-8: Read DMA Status Interface from Read DMA Engine to Descriptor Controller
Signal Name
Direction
Description
RdAstTxData_o[31:0]
Output
Drives status information to the Descriptor Controller
component. Refer to DMA Status Bus table below for more
information
RdAstTxValid_o
Output
When asserted, indicates that
RdAstTxData_o[31:0]
is valid.
Table 5-9: Write DMA Status Interface from Write DMA Engine to Descriptor Controller
Signal Name
Direction
Description
WrAstTxData_o[31:0]
Output
Drives status information to the Descriptor Controller
component. Refer to DMA Status Bus table below for more
information about this bus.
WwAstTxValid_o
Output
When asserted, indicates that
WrAstTxData_o[31:0]
is valid.
Table 5-10: DMA Descriptor Format
Bits
Name
Description
[31:0]
Source Low Address
Low-order 32 bits of the DMA source address. The address
boundary must align to the 32 bits so that the 2 least significant
bits are 2'b00. For the Read DMA module the source address is
the PCIe domain address. For the Write DMA module the source
address is the Avalon-MM domain address. You must program
the low-order 32 bits of the address after you program the high-
order 32 bits.
[63:32]
Source High Address
High-order 32 bits of the source address.
[95:64]
Destination Low Address
Low-order 32 bits of the DMA destination address. The address
boundary must align to the 32 bits so that the 2 least significant
bits have the value of 2'b00. For the Read DMA module, the
destination address is the Avalon-MM domain address. For the
Write DMA module the destination address is the PCIe domain
address.
[127:96]
Destination High
Address
High-order 32 bits of the destination address.
[145:12
8]
DMA Length
Specifies DMA length in DWords. The length must be greater
than 0. The maximum length is 1 MByte - 4 bytes.
5-10
Avalon-ST Descriptor Status Interface when Instantiated Separately
UG-01145_avmm_dma
2015.05.14
Altera Corporation
IP Core Interfaces