Altera Arria 10 Avalon-MM DMA - Manual (Page 123)

The DMA modules shown in the block diagrams implement the following functionality:
• Read DMA –The Read DMA module sends memory read TLPs upstream and writes the completion
data to external Avalon-MM components using the high throughput read master port. It follows the
PCI Express Base Specification rules concerning tags, flow control credits, completion timeouts, read
completion boundary, and 4 KByte boundaries.
• Write DMA –The Write DMA module reads data from the external Avalon-MM slave and sends it
upstream forming memory write TLPs. It follows the PCI Express Base Specification rules concerning
tags, flow control credits, completion timeouts, RX buffer completion rules, and 4 KByte boundaries.
• DMA Descriptor Controller–The Descriptor Control module manages Read and Write DMA
operations. Host software programs its internal registers with the location of the descriptor table
residing in the PCI Express main memory. Based on this information, the descriptor control logic
directs the DMA Read module to copy the entire table and place it in the local FIFO. It then fetches the
table entries and directs the DMA to transfer the data between the Avalon and PCIe domains one
descriptor at a time. It also sends DMA status upstream via the TX slave port. For more information
about the Descriptor Control module registers, refer to DMA Descriptor Controller Registers on
page 6-15.
• RX Master–You can select either a single dword or high-performance bursting RX Master module.
This RX master port receives read and write TLPs from the host and translates them to Avalon-MM
requests in the Qsys system. This module allows host software to access other Avalon-MM slaves
connected in the Qsys system. It can also access the Descriptor Controller if it is externally instanti‐
ated.
• TX Slave–The TX Slave module supports single dword read and write requests. Avalon-MM masters
can use this slave port to access PCI Express memory space. The DMA Descriptor Controller uses this
path to update the DMA status upstream, including MSI requests.
Related Information
• Getting Started with the Avalon-MM DMA on page 2-1
• DMA Descriptor Controller Registers on page 6-15
UG-01145_avmm_dma
2015.05.14
Arria 10 Avalon-MM DMA for PCI Express 9-11
IP Core Architecture Altera Corporation
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