Write descriptor controller avalon-mm master port, Read descriptor table avalon-mm slave port – Altera Arria 10 Avalon-MM DMA User Manual
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Signal Name
Direction
Description
RdDCMRead_o
Output
When asserted, indicates a read transaction.
RdDCMWaitRequest_i
Input
When asserted, indicates that the Avalon-MM slave devices is
not ready to respond.
RdDCMWriteData_
o[31:0]
Output
Drives the single dword write data to the connected slave port.
RdDCMWrite_o
Output
When asserted, indicates a write transaction.
Write Descriptor Controller Avalon-MM Master Port
Table 5-13: Write Descriptor Controller Avalon-MM Master Interface
The Avalon-MM Descriptor Controller Master interface is a 32-bit single-dword master with wait request
support. The Write Descriptor Controller uses this port to write status back to the PCI-Express domain and
possibly MSI when MSI messages are enabled.
Signal Name
Direction
Description
WrDCMAddress_o[63:0]
Output
Specifies the address for the write data.
WrDCMByteEnable_
o[3:0]
Output
Specifies which data bytes are valid.
WrDCMReadDataValid_i
Input
When asserted, indicates that the read data is valid.
WrRdDCMReadData_
o[31:0]
Output
Holds the single dword read data.
WrDCMRead_o
Output
When asserted, indicates a read transaction.
WrDCMWaitRequest_i
Input
When asserted, indicates that the Avalon-MM slave device is not
ready to respond.
WrDCMWriteData_
o[31:0]
Output
Drives the single dword write data.
WrDCMWrite_o
Output
When asserted, indicates a write transaction.
Read Descriptor Table Avalon-MM Slave Port
This port is available when you select the internal Descriptor Controller. It receives the Read DMA
descriptors which are fetched by Read DMA. . Connect the port to the Read DMA Avalon-MM master
port.
5-12
Write Descriptor Controller Avalon-MM Master Port
UG-01145_avmm_dma
2015.05.14
Altera Corporation
IP Core Interfaces