Altera Arria 10 Avalon-MM DMA - Manual (Page 73)

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification
0x034 Reserved, Capabilities PTR Type 0 Configuration Space Header
Type 1 Configuration Space Header
0x038 Reserved N/A
0x03C Interrupt Pin, Interrupt Line
Bridge Control, Interrupt Pin, Interrupt Line Type 0 Configuration Space Header
Type 1 Configuration Space Header
0x050 MSI-Message Control Next Cap Ptr
Capability ID
MSI and MSI-X Capability Structures
0x054 Message Address MSI and MSI-X Capability Structures
0x058 Message Upper Address MSI and MSI-X Capability Structures
0x05C Reserved Message Data MSI and MSI-X Capability Structures
0x068 MSI-X Message Control Next Cap Ptr
Capability ID
MSI and MSI-X Capability Structures
0x06C MSI-X Table Offset BIR MSI and MSI-X Capability Structures
0x070 Pending Bit Array (PBA) Offset BIR MSI and MSI-X Capability Structures
0x078 Capabilities Register Next Cap PTR Cap ID PCI Power Management Capability
Structure
0x07C Data PM Control/Status Bridge Extensions
Power Management Status & Control
PCI Power Management Capability
Structure
0x800 PCI Express Enhanced Capability Header Advanced Error Reporting Enhanced
Capability Header
0x804 Uncorrectable Error Status Register Uncorrectable Error Status Register
0x808 Uncorrectable Error Mask Register Uncorrectable Error Mask Register
0x80C Uncorrectable Error Severity Register Uncorrectable Error Severity Register
0x810 Correctable Error Status Register Correctable Error Status Register
0x814 Correctable Error Mask Register Correctable Error Mask Register
6-4 Correspondence between Configuration Space Registers and the PCIe...
UG-01145_avmm_dma
2015.05.14
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