Altera Arria 10 Avalon-MM DMA - Manual (Page 67)

Signal Direction Description
txelecidle0
Output Transmit electrical idle <n>. This signal forces the TX output to
electrical idle.
tx_margin0[2:0]
Output Transmit V
OD
margin selection. The value for this signal is based
on the value from the
Link Control 2 Register
. Available for
simulation only.
txswing0 Output When asserted, indicates full swing for the transmitter voltage.
When deasserted indicates half swing.
txsynchd0[1:0] Output For Gen3 operation, specifies the block type. The following
encodings are defined:
• 2'b01: Ordered Set Block
• 2'b10: Data Block
5-26 PIPE Interface Signals
UG-01145_avmm_dma
2015.05.14
Altera Corporation IP Core Interfaces
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