Altera Arria 10 Avalon-MM DMA - Manual (Page 3)

Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates............................................4-5
Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate...................................... 4-7
IP Core Interfaces ...............................................................................................5-1
Arria 10 DMA Avalon-MM DMA Interface to the Application Layer................................................5-1
Read DMA Avalon-MM Master Port .......................................................................................... 5-3
Write DMA Avalon-MM Master Port .........................................................................................5-5
RX Master Module ..........................................................................................................................5-5
TX Slave Module .............................................................................................................................5-7
32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals .................5-8
Avalon-ST Descriptor Control Interface when Instantiated Separately ................................. 5-9
Descriptor Controller Interfaces when Instantiated Internally ..............................................5-11
Clock Signals ..............................................................................................................................................5-14
Reset, Status, and Link Training Signals.................................................................................................5-14
MSI Interrupts for Endpoints ................................................................................................................. 5-19
Hard IP Reconfiguration Interface .........................................................................................................5-20
Physical Layer Interface Signals ..............................................................................................................5-22
Serial Data Signals .........................................................................................................................5-22
PIPE Interface Signals .................................................................................................................. 5-22
Test Signals .................................................................................................................................... 5-27
Registers...............................................................................................................6-1
Correspondence between Configuration Space Registers and the PCIe Specification ..................... 6-1
Type 0 Configuration Space Registers ..................................................................................................... 6-5
PCI Express Capability Structures.............................................................................................................6-6
Altera-Defined VSEC Registers................................................................................................................. 6-8
CvP Registers................................................................................................................................................ 6-9
Uncorrectable Internal Error Mask Register ........................................................................................ 6-12
Uncorrectable Internal Error Status Register ....................................................................................... 6-13
Correctable Internal Error Mask Register .............................................................................................6-14
Correctable Internal Error Status Register ............................................................................................6-14
DMA Descriptor Controller Registers ...................................................................................................6-15
Read DMA and Write DMA Descriptor Format ..................................................................... 6-21
Read DMA Example .....................................................................................................................6-22
Software Program for Simultaneous Read and Write DMA .................................................. 6-25
Control Register Access (CRA) Avalon-MM Slave Port .....................................................................6-26
Arria 10 Reset and Clocks................................................................................... 7-1
Reset Sequence for Hard IP for PCI Express IP Core and Application Layer ....................................7-2
Clocks ........................................................................................................................................................... 7-4
Clock Domains ................................................................................................................................7-4
Clock Summary ...............................................................................................................................7-5
Error Handling ................................................................................................... 8-1
Physical Layer Errors ..................................................................................................................................8-2
TOC-3
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