Altera Arria 10 Avalon-MM DMA - Manual (Page 87)

Address
Offset
Register Access Description
0x000
C
EP Read Descriptor FIFO Base
(High)
RW Specifies the upper 32 bits of the base
address of the read descriptor table in
Endpoint Avalon-MM memory. The Read
DMA fetches the descriptors from Root
Complex memory and writes the descrip‐
tors to the FIFO at this location and writes
the descriptors to the FIFO at this
location. This must be the Avalon-MM
address of the descriptor controller's Read
Descriptor Table Avalon-MM Slave Port
as seen by the Read DMA Avalon-MM
Master Port. You must program this
register before programming the lower 32
bits of this register.
0x001
0
RD_DMA_LAST_PTR RW When read, returns the ID of the last
descriptor requested. If no DMA request
is outstanding or the DMA is in reset,
returns a value 0xFF.
When written, specifies the ID of the last
descriptor requested. The difference
between the value read and the value
written is the number of descriptors to be
processed.
For example, if the value reads 4, the last
descriptor requested is 4. To specify 5
more descriptors, software should write a
9 into the
RD_DMA_LAST_PTR
register. The
DMA executes 5 more descriptors.
The descriptor ID loops back to 0 after
reaching
RD_TABLE_SIZE
. For example, if
the
RD_TABLE_SIZE
value read is 126 and
you want to execute three more descrip‐
tors, software must write 127, and then 1
into the
RD_DMA_LAST_PTR
register.
0x001
4
RD_TABLE_SIZE RW
Specifies the size of the Read descriptor
table. Set to the number of descriptors - 1.
By default,
RD_TABLE_SIZE
is set to
127.This value specifies the last
Descriptor ID
.
6-18 DMA Descriptor Controller Registers
UG-01145_avmm_dma
2015.05.14
Altera Corporation Registers
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