Altera Arria 10 Avalon-MM DMA - Manual (Page 99)

Byte Offset
Register Dir Description
14'h006C
lane_act_reg[3:0] O Lane Active Mode: This signal indicates the number
of lanes that configured during link training. The
following encodings are defined:
• 4’b0001: 1 lane
• 4’b0010: 2 lanes
• 4’b0100: 4 lanes
• 4’b1000: 8 lanes
6-30 Control Register Access (CRA) Avalon-MM Slave Port
UG-01145_avmm_dma
2015.05.14
Altera Corporation Registers
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