Data Link Layer Errors ...............................................................................................................................8-2
Transaction Layer Errors ........................................................................................................................... 8-3
Error Reporting and Data Poisoning ....................................................................................................... 8-5
Uncorrectable and Correctable Error Status Bits ...................................................................................8-6
IP Core Architecture........................................................................................... 9-1
Top-Level Interfaces ...................................................................................................................................9-3
Avalon-MM DMA Interface.......................................................................................................... 9-3
Clocks and Reset ............................................................................................................................. 9-3
Interrupts ......................................................................................................................................... 9-3
PIPE .................................................................................................................................................. 9-3
Data Link Layer ...........................................................................................................................................9-4
Physical Layer ..............................................................................................................................................9-6
Arria 10 Avalon-MM DMA for PCI Express ..........................................................................................9-8
Design Implementation.................................................................................... 10-1
Making Pin Assignments to Assign I/O Standard to Serial Data Pins ..............................................10-1
Recommended Reset Sequence to Avoid Link Training Issues ......................................................... 10-1
SDC Timing Constraints.......................................................................................................................... 10-2
Frequently Asked Questions.............................................................................. A-1
Additional Information......................................................................................B-1
Revision History for the Avalon-MM Interface with DMA..................................................................B-1
How to Contact Altera................................................................................................................................B-4
Typographic Conventions..........................................................................................................................B-5
TOC-4
Altera Corporation
