Datasheet, Datasheet -1 – Altera Arria 10 Avalon-MM DMA User Manual
Page 5
Datasheet
1
2015.05.14
UG-01145_avmm_dma
Arria 10 Avalon-MM DMA Interface for PCIe Datasheet
Altera
®
Arria 10 FPGAs include a configurable, hardened protocol stack for PCI Express
®
that is
compliant with PCI Express Base Specification 3.0.
The Arria
®
10 Hard IP for PCI Express with the Avalon
®
Memory-Mapped (Avalon-MM) DMA
interface removes some of the complexities associated with the PCIe protocol. For example, the IP core
handles TLP encoding and decoding. In addition, the IP core includes Read DMA and Write DMA
engines. If you have already architected your own DMA system with the Avalon-MM interface, you may
want to continue to use that system. However, you may benefit from the simplicity of having the included
DMA engines. New users of this protocol should use this IP core. This variant is available in Qsys for 128-
and 256-bit interfaces to the Application Layer. The Avalon-MM interface and DMA engines are
implemented in FPGA soft logic.
Figure 1-1: Arria 10 PCIe Variant with Avalon-MM DMA Interface
The following figure shows the high-level modules and connecting interfaces for this variant.
Bridge
and DMA
Engine
PCIe Hard IP
Block
PIPE
Interface
PHY IP Core
for PCIe
(PCS/PMA)
Serial Data
Transmission
Application
Layer
(User Logic)
Avalon-MM with
DMA Interface
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