Altera Arria 10 Avalon-MM DMA User Manual
Page 45
The Read DMA Avalon-MM Master Port interface performs two functions:
• Provides the descriptor table to the Descriptor Controller: This module sends memory read requests to
fetch the descriptor table from host memory using upstream memory read requests on the Avalon-ST
read interface. This module writes the descriptor entries in to the Descriptor Controller FIFO using
this 128- or 256- bit Avalon-MM interface.
• Writes data to memory located in Avalon-MM space: After a DMA Read finishes fetching data from
the source address in host memory via normal DMA-Read operation, the Read DMA module writes
the data to the destination address in Avalon-MM address space via this interface.
Table 5-1: Read DMA 256-Bit Avalon-MM Master Interface
Signal Name
Direction
Description
RdDmaWrite_o
Output When asserted, indicates that the Read DMA module is
ready to write read completion data to a memory
component in the Avalon-MM address space.
RdDmaAddress_o[63:0]
Output Specifies the write address in the Avalon-MM address
space for the read completion data.
RdDmaWriteData_o[127 or
255:0]
Output The read completion data to be written to the
Avalon-MM address space.
RdDmaBurstCount_o[4:0] or
[5:0]
Output Specifies the burst count in 128- or 256-bit words. This
bus is 5 bits for the 256-bit interface. It is 6 bits for the
128-bit interface.
RdDmaByteEnable_o[15 or
31:0]
Output Specifies which bytes of a 128- or 256-bit word are valid.
RdDmaWaitRequest_i
Input
When asserted, indicates that the memory is not ready to
receive data.
Frequent assertion may incoming packet processing to
stop until
RdDmaWaitRequest_i
deasserts.
Figure 5-3: Read DMA Avalon-MM Master Writes Data to FPGA Memory
read_data_mover\.RdDmaAddress_o[63:0]
read_data_mover\.RdDmaBurstCount_o[4:0]
read_data_mover\.RdDmaWrite_o
read_data_mover\.RdDmaWaitRequest_i
read_data_mover\.RdDmaWriteData_o[255:0]
read_data_mover\.RdDmaByteEnable_o[31:0]
100
080
100
180
200
280
300
380
.
.
.
.
.
.
.
.
5-4
Read DMA Avalon-MM Master Port
UG-01145_avmm_dma
2015.05.14
Altera Corporation
IP Core Interfaces