Altera Arria 10 Avalon-MM DMA User Manual
Page 93
This is the upper 32 bits of the destination address.
d. Program 0 to destination address 0xF000_0208.
This is the lower 32 bits of the destination address.
e. Program 0x0003_FFFF to 0xF000_0210 to transfer 1 MByte of data for descriptor ID 0.
4. Repeat this procedure for the second data block:
a. Program 0x2000_0000 to source address 0xF000_0224.
b. Program 0x0000_0000 to source address 0xF000_0220.
c. Program 0x0001_0000 to destination address 0xF000_022C.
d. Program 0x0000_0000 to destination address 0xF000_0228.
e. Program 0x0005_FFFF to 0xF000_0230 to transfer 512 KBytes of data for descriptor ID 1.
5. Repeat this procedure for the third data block:
a. Program 0x2000_0000 to source address 0xF000_024C.
b. Program 0x0000_0001 to source address 0xF000_0248.
c. Program 0x1000_0000 to destination address 0xF000_0254.
d. Program 0x0000_0000 to destination address 0xF000_0250.
e. Program 0x0005_FFFF to 0xF000_0250 to transfer 256 KBytes of data for descriptor ID 2.
6. Program the DMA Descriptor Controller with the address of the status and descriptor table in the PCI
Express address space. The Read DMA registers start at offset 0.
a. Program 0x0 to offset 0x4.
This is the upper 32 bits of the PCIe memory where the status and descriptor table is stored.
b. Program 0xF000_0000 to offset 0x0.
This is the lower 32 bits of the address in PCIe memory that stores the status and descriptor tables.
The Read DMA automatically adds an offset of 0x200 to this value to start the copy after the status
table.
7. Program the DMA Descriptor Controller with the on-chip FIFO address. This is the address to which
the Descriptor Controller will copy the status and descriptor table.
a. Program 0x0 to offset 0xC
This is the upper 32 bits of the on-chip FIFO address in the Avalon-MM address domain.
b. Program 0xc000_0000 to offset 0x8.
This is the lower 32 bits of the on-chip FIFO address. This is address of the internal on-chip FIFO
that is a part of the Descriptor Controller as seen by the RX Master.
8. Program the Descriptor Controller
RD_DMA_LAST_PTR
register.
This step starts the DMA. It also specifies the status dword to be updated when the three descriptors
complete.
• To update a single
done
bit for the final descriptor, program 0x2 to offset 0x10. The Descriptor
Controller processes all three descriptors and writes the
done
bit to 0xF000_0008 of the status table.
• To update the
done
bits for all three descriptors, program 0x10 three times with the values 0, 1, and
2. The Descriptor Controller sets the
done
bits for addresses 0xF000_0000, 0xF000_0004, and
0xF000_0008. If the system supports out-of-order Read Completions, the Descriptor Controller
may complete descriptors out of order. In such systems, you must use this method of requesting
done
status for each descriptor. Software must check for
done
status for every descriptor.
6-24
Read DMA Example
UG-01145_avmm_dma
2015.05.14
Altera Corporation
Registers