Document Outline

• SECTION 1 – OVERVIEW
• SECTION 2 – ARCHITECTURE
  • 2.1 – Instruction Decoding
  • 2.2 – Register Space
  • 2.3 – Memory Types
    • 2.3.1 – Flash Memory
    • 2.3.2 – SRAM Memory
    • 2.3.3 – Utility ROM
    • 2.3.4 – Stack Memory
  • 2.4 – Program and Data Memory Mapping and Access
    • 2.4.1 – Program Memory Access
    • 2.4.2 – Program Memory Mapping
    • 2.4.3 – Data Memory Access
    • 2.4.4 – Data Memory Mapping
  • 2.5 – Data Alignment
  • 2.6 – Reset Conditions
    • 2.6.1 – Power-On/Brownout Reset
    • 2.6.2 – Watchdog Timer Reset
    • 2.6.3 – External Reset
    • 2.6.4 – Internal System Resets
    • 2.6.5 – Software Reset
  • 2.7 – Clock Generation
• SECTION 3 – SYSTEM REGISTER DESCRIPTIONS
  • 3.1 – Accumulator Pointer Register (AP, 08h[00h])
  • 3.2 – Accumulator Pointer Control Register (APC, 08h[01h])
  • 3.3 – Processor Status Flags Register (PSF, 08h[04h])
  • 3.4 – Interrupt and Control Register (IC, 08h[05h])
  • 3.5 – Interrupt Mask Register (IMR, 08h[06h])
  • 3.6 – System Control Register (SC, 08h[08h])
  • 3.7 – Interrupt Identification Register (IIR, 08h[0Bh])
  • 3.8 – Watchdog Control Register (WDCN, 08h[0Fh])
  • 3.9 – Accumulator n Register (A[n], 09h[nh])
  • 3.11 – Instruction Pointer Register (IP, 0Ch[00h])
  • 3.12 – Stack Pointer Register (SP, 0Dh[01h])
  • 3.13 – Interrupt Vector Register (IV, 0Dh[02h])
  • 3.14 – Loop Counter 0 Register (LC[0], 0Dh[06h])
  • 3.15 – Loop Counter 1 Register (LC[1], 0Dh[07h])
  • 3.16 – Frame Pointer Offset Register (OFFS, 0Eh[03h])
  • 3.17 – Data Pointer Control Register (DPC, 0Eh[04h])
  • 3.18 – General Register (GR, 0Eh[05h])
  • 3.19 – General Register Low Byte (GRL, 0Eh[06h])
  • 3.20 – Frame Pointer Base Register (BP, 0Eh[07h])
  • 3.21 – General Register Byte-Swapped (GRS, 0Eh[08h])
  • 3.22 – General Register High Byte (GRH, 0Eh[09h])
  • 3.23 – General Register Sign Extended Low Byte (GRXL, 0Eh[0Ah])
  • 3.24 – Frame Pointer Register (FP, 0Eh[0Bh])
  • 3.25 – Data Pointer 0 Register (DP[0], 0Fh[03h])
  • 3.26 – Data Pointer 1 Register (DP[1], 0Fh[07h])
• SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS
  • 4.1 – Module 0 Peripheral Registers
  • 4.2 – Module 1 Peripheral Registers
  • 4.3 – Module 2 Peripheral Registers
  • 4.4 – Module 3 Peripheral Registers
  • 4.5 – Module 4 Peripheral Registers
  • 4.6 – Module 5 Peripheral Registers
• SECTION 5 – INTERRUPTS
  • 5.1 – Servicing Interrupts
  • 5.2 – Module Interrupt Identification Registers
  • 5.3 – Interrupt System Operation
    • 5.3.1 – Synchronous vs. Asynchronous Interrupt Sources
    • 5.3.2 – Interrupt Prioritization by Software
    • 5.3.3 – Interrupt Exception Window
• SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC)
  • 6.1 – Detailed Description
    • 6.1.1 – Reference Selection
  • 6.2 – DAC Register Descriptions
    • 6.2.1 – DAC Configuration Register (DACCFG)
    • 6.2.2 – DAC Data Registers (DACD0-DACD7)
    • 6.2.3 – Reference Pin Configuration Register (RPCFG)
  • 6.3 – DAC Code Examples
• SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC)
  • 7.1 – Detailed Description
    • 7.1.1 – ADC Controller
    • 7.1.2 – ADC Conversion Sequencing
    • 7.1.3 – Internal Die Temperature Conversion
    • 7.1.4 – Sample and Hold Conversion
    • 7.1.5 – ADC Frame Sequence
    • 7.1.6 – ADC Reference
    • 7.1.7 – ADC Conversion Time
    • 7.1.8 – Location Override
    • 7.1. 9 – Averaging
    • 7.1.10 – ADC Data Reading
    • 7.1.11 – ADC Interrupts
    • 7.1.12 – ADC Internal Offset
    • 7.1.13 – DAC External Reference Pins (REFINA and REFINB) as ADC Channels
    • 7.1.14 – Fast Conversion Mode (ADST.ENABLE_2X)
  • 7.2 – ADC Register Descriptions
    • 7.2.1 – ADC Control Register (ADCN)
    • 7.2.2 – ADC Status Register (ADST)
    • 7.2.3 – PIN Select Register (PINSEL)
    • 7.2.4 – ADC Status Register (ADST1)
    • 7.2.5 – ADC Address Register (ADADDR)
    • 7.2.6 – ADC Data and Configuration Register (ADDATA)
    • 7.2.7 – Reference Pin Configuration Register (RPCFG)
    • 7.2.8 – Temperature Control Register (TEMPCN)
    • 7.2.9 – Average and Reference Control Register (REFAVG)
    • 7.2.10 – ADC Voltage Offset Register (ADVOFF)
    • 7.2.11 – ADC Voltage Scale Trim Registers (ADCG1, ADCG2, ADCG3 and ADCG4)
  • 7.3 – ADC Code Examples
• SECTION 8 – SAMPLE AND HOLD
  • 8.1 – Detailed Description
    • 8.1.1 – Operation
    • 8.1.2 – Fast Mode Operation
    • 8.1.3 – Sampling Control
    • 8.1.4 – Pin Capacitance Discharge
    • 8.1.5 – Sample and Hold Data Reading
    • 8.1.6 – Sample and Hold Interrupts
  • 8.2 – Sample and Hold Register Descriptions
• SECTION 9 – QUICK TRIP (FAST COMPARATOR)
  • 9.1 – Detailed Description
    • 9.1.1 – Quick Trip List Sequencing
    • 9.1.2 – Operation
    • 9.1.3 – Setting Quick Trip Thresholds
    • 9.1.4 – Quick Trip Interrupts
  • 9.2 – Quick Trip Register Descriptions
• SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE
  • 10.1 – Detailed Description
    • 10.1.1 – Description of Master I2C Interface
    • 10.1.2 – Default Operation
    • 10.1.3 – I2C Clock Generation
    • 10.1.4 – Timeout
    • 10.1.5 – Generating a START
    • 10.1.6 – Generating a STOP
    • 10.1.7 – Transmitting a Slave Address
    • 10.1.8 – Transmitting Data
    • 10.1.9 – Receiving Data
    • 10.1.10 – I2C Master Clock Stretching
    • 10.1.11 – Resetting the I2C Master Controller
    • 10.1.12 – Alternate Location
    • 10.1.13 – Operation as a Slave
    • 10.1.14 – GPIO
  • 10.2 – I2C Master Controller Register Description
• SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE
  • 11.1 – Detailed Description
    • 11.1.1 – Default Operation
    • 11.1.2 – Slave Addresses
    • 11.1.3 – I2C START Detection
    • 11.1.4 – I2C STOP Detection
    • 11.1.5 – Slave Address Matching
    • 11.1.6 – Advanced Mode Operation RX FIFO and TX Pages
    • 11.1.7 – Transmitting Data
    • 11.1.8 – Receiving Data
    • 11.1.9 – Clock Stretching
    • 11.1.10 – SMBus Timeout
    • 11.1.11 – Resetting the I2C Slave Controller
  • 11.2 – I2C Slave Controller Register Description
• SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI)
  • 12.1 – Serial Peripheral Interface (SPI) Detailed Description
  • 12.1.1 – SPI Transfer Formats
  • 12.1.2 – SPI Character Lengths
  • 12.2 – SPI System Errors
  • 12.2.1 – Mode Fault
  • 12.2.2 – Receive Overrun
  • 12.2.3 – Write Collision While Busy
  • 12.3 – SPI Interrupts
  • 12.4 – SPI Master
  • 12.4.1 – SPI Transfer Baud Rates
  • 12.4.2 – SPI Master Operation
  • 12.4.3 – SPI Master Register Descriptions
  • 12.5 – SPI Slave
    • 12.5.1 – SPI Slave Select
    • 12.5.2 – SPI Transfer Baud Rates
    • 12.5.3 – SPI Slave Operation
  • 12.5.4 – SPI Slave Register Descriptions
• SECTION 13 – 3-WIRE
  • 13.1 – Detailed Description
    • 13.1.1 – Operation
  • 13.2 – 3-Wire Register Descriptions
• SECTION 14 – PWM
  • 14.1 – Detailed Description
    • 14.1.1 – PWMCN and PWMDATA SFRs
    • 14.1.2 – PWMSYNC SFR
  • 14.2 – Individual PWM Channel Operation
    • 14.2.1 – Duty Cycle Register (DCYCn)
    • 14.2.2 – PWM Configuration Register (PWMCFGn)
    • 14.2.3 – PWM DELAY Register (PWMDLYn)
  • 14.3 – PWM Output Register Descriptions
  • 14.4 – PWM Output Code Examples
• SECTION 15 – GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS
  • 15.1 – Overview
  • 15.2 – GPIO Port Register Descriptions
    • 15.2.1 – GPIO Direction Register Port (PD0, PD1, PD2, and PD6)
    • 15.2.2 – GPIO Output Register Port (PO0, PO1, PO2, and PO6)
    • 15.2.3 – GPIO Input Register for Port (PI0, PI1, PI2, and PI6)
    • 15.2.4 – GPIO Port External Interrupt Edge Select Register (EIES0, EIES1, EIES2, and EIES6)
    • 15.2.5 – GPIO Port External Interrupt Flag Register (EIF0, EIF1, EIF2, and EIF6)
    • 15.2.6 – GPIO Port External Interrupt Enable Register (EIE0, EIE1, EIE2, and EIE6)
  • 15.3 – GPIO Code Example
    • 15.3.1 – GPIO Pin as Output
    • 15.3.2 – GPIO High-Impedance Input
    • 15.3.3 – GPIO Weak Pullup Input
    • 15.3.4 – GPIO Open-Drain Output
• SECTION 16 – GENERAL-PURPOSE TIMERS
  • 16.1 – Detailed Description
    • 16.1.1 – Timer Modes
    • 16.1.2 – Clock Selection
    • 16.1.3 – Timer Clock Prescaler
  • 16.2 – Timer Register Descriptions
• SECTION 17 – SUPPLY VOLTAGE MONITOR (SVM)
• SECTION 18 – HARDWARE MULTIPLIER MODULE
  • 18.1 – Hardware Multiplier Organization
  • 18.2 – Hardware Multiplier Controls
  • 18.3 – Register Output Selection
    • 18.3.1 – Signed-Unsigned Operand Selection
    • 18.3.2 – Operand Count Selection
  • 18.4 – Hardware Multiplier Operations
    • 18.4.1 – Accessing the Multiplier
  • 18.5 – Hardware Multiplier Peripheral Registers
  • 18.6 – Hardware Multiplier Examples
• SECTION 19 – WATCHDOG TIMER
  • 19.1 - Overview
  • 19.2 – Watchdog Timer Description
    • 19.2.1 – Watchdog Timer Interrupt Operation
    • 19.2.2 – Watchdog Timer Reset Operation
    • 19.2.3 – Watchdog Timer Applications
• SECTION 20 – TEST ACCESS PORT (TAP)
  • 20.1 – TAP Controller
  • 20.2 – TAP State Control
    • 20.2.1 – Test-Logic-Reset
    • 20.2.2 – Run-Test-Idle
    • 20.2.3 – IR-Scan Sequence
    • 20.2.4 – DR-Scan Sequence
  • 20.3 – Communication via TAP
    • 20.3.1 – TAP Communication Examples – IR-Scan and DR-Scan
• SECTION 21 – IN-CIRCUIT DEBUG MODE
  • 21.1 – Background Mode Operation
    • 21.1.1 – Breakpoint Registers
    • 21.1.2 – Using Breakpoints
  • 21.2 – Debug Mode
    • 21.2.1 – Debug Mode Commands
    • 21.2.2 – Read Register Map Command Host-ROM Interaction
    • 21.2.3 – Single Step Operation (Trace)
    • 21.2.4 – Return
    • 21.2.5 – Debug Mode Special Considerations
  • 21.3 – In-Circuit Debug Peripheral Registers
• SECTION 22 – IN-SYSTEM PROGRAMMING
  • 22.1 – Detailed Description
    • 22.1.1 – Password Protection
    • 22.1.2 – Entering JTAG Bootloader
    • 22.1.3 – Entering I2C Bootloader
    • 22.1.4 – I2C Bootloader Disable
  • 22.2 – Bootloader Operation
    • 22.2.1 – JTAG Bootloader Protocol
    • 22.2.2 – I2C Bootloader Protocol
  • 22.3 – Bootloader Commands
    • 22.3.1 – Command 00h – No Operation
    • 22.3.2 – Command 01h – Exit Loader
    • 22.3.3 – Command 02h – Master Erase
    • 22.3.4 – Command 03h – Password Match
    • 22.3.5 – Command 04h – Get Status
    • 22.3.6 – Command 05h – Get Supported Commands
    • 22.3.7 – Command 06h – Get Code Size
    • 22.3.8 – Command 07h – Get Data Size
    • 22.3.9 – Command 08h – Get Loader Version
    • 22.3.10 – Command 09h – Get Utility ROM Version
    • 22.3.11 – Command 10h – Load Code
    • 22.3.12 – Command 11h – Load Data
    • 22.3.13 – Command 20h – Dump Code
    • 22.3.14 – Command 21h – Dump Data
    • 22.3.15 – Command 30h – CRC Code
    • 22.3.16 – Command 31h – CRC Data
    • 22.3.17 – Command 40h – Verify Code
    • 22.3.18 – Command 41h – Verify Data
    • 22.3.19 – Command 50h – Load and Verify Code
    • 22.3.20 – Command 51h – Load and Verify Data
    • 22.3.21 – Command E0h – Code Page Erase
• SECTION 23 – PROGRAMMING
  • 23.1 – Addressing Modes
  • 23.2 – Prefixing Operations
  • 23.3 – Reading and Writing Registers
    • 23.3.1 – Loading an 8-Bit Register with an Immediate Value
    • 23.3.2 – Loading a 16-Bit Register with a 16-Bit Immediate Value
    • 23.3.3 – Moving Values Between Registers of the Same Size
    • 23.3.4 – Moving Values Between Registers of Different Sizes
  • 23.4 – Reading and Writing Register Bits
  • 23.5 – Using the Arithmetic and Logic Unit
    • 23.5.1 – Selecting the Active Accumulator
    • 23.5.2 – Enabling Auto-Increment and Auto-Decrement
    • 23.5.3 – ALU Operations Using the Active Accumulator and a Source
    • 23.5.4 – ALU Operations Using Only the Active Accumulator
    • 23.5.5 – ALU Bit Operations Using Only the Active Accumulator
    • 23.5.6 – Example: Adding Two 4-Byte Numbers Using Auto-Increment
  • 23.6 – Processor Status Flag Operations
    • 23.6.1 – Sign Flag
    • 23.6.2 – Zero Flag
    • 23.6.3 – Equals Flag
    • 23.6.4 – Carry Flag
    • 23.6.5 – Overflow Flag
  • 23.7 – Controlling Program Flow
    • 23.7.1 – Obtaining the Next Execution Address
    • 23.7.2 – Unconditional Jumps
    • 23.7.3 – Conditional Jumps
    • 23.7.4 – Calling Subroutines
    • 23.7.5 – Looping Operations
    • 23.7.6 – Conditional Returns
  • 23.8 – Handling Interrupts
    • 23.8.1 – Conditional Return from Interrupt
  • 23.9 – Accessing the Stack
  • 23.10 – Accessing Data Memory
• SECTION 24 – INSTRUCTION SET
• SECTION 25 – UTILITY ROM
  • 25.1 – Overview
  • 25.2 – In-Application Programming Functions
    • 25.2.1 – UROM_flashWrite
    • 25.2.2 – UROM_flashErasePage
  • 25.3 – Data Transfer Functions
    • 25.3.1 – UROM_moveDP0
    • 25.3.2 – UROM_moveDP0inc
    • 25.3.3 – UROM_moveDP0dec
    • 25.3.4 – UROM_moveDP1
    • 25.3.5 – UROM_moveDP1inc
    • 25.3.6 – UROM_moveDP1dec
    • 25.3.7 – UROM_moveBP
    • 25.3.8 – UROM_moveBPinc
    • 25.3.9 – UROM_moveBPdec
    • 25.3.10 – UROM_copyBuffer
  • 25.4 Special Functions
    • 25.4. 1 – UROM_copyWord
    • 25.4. 2 – Software Reset
  • 25.5 – Utility ROM Examples
    • 25.5.1 – Reading Constant Word Data from Flash
    • 25.5.2 – Reading Constant Byte Data from Flash (Indirect Function Call)
• SECTION 26 – MISCELLANEOUS
  • 26.1 – Overview
  • 26.2 – CRC8
    • 26.2.1 – CRC Data In (CRC8IN)
    • 26.2.2 – CRC Data Out (CRC8OUT)
    • 26.2.3 – Example
  • 26.3 – Software Interrupts
    • 26.3.1 – User Interrupt Register (USER_INT)
  • 26.4 – General-Purpose Registers
    • 26.4.1 – General-Purpose Register
  • 26.5 – Device Number and I2C Bootloader Address Disable
    • 26.5.1 – Device Number Register (DEV_NUM)