Avalon-st verilog hdl testbench -1 – Altera Avalon Verification IP Suite User Manual

Page 10

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event_instruction_inconsistent() ................................................................................................15-3
event_instruction_unchanged() .................................................................................................15-3
event_result_driven() ...................................................................................................................15-4

event_result_done() ......................................................................................................................15-4

event_unknown_instruction_received() ...................................................................................15-4

get_ci_clk_en() ..............................................................................................................................15-5

get_instruction_a() .......................................................................................................................15-5

get_instruction_b() .......................................................................................................................15-5

get_instruction_c() .......................................................................................................................15-5

get_instruction_dataa() ................................................................................................................15-6

get_instruction_datab() ...............................................................................................................15-6

get_instruction_idle() ...................................................................................................................15-6

get_instruction_n() .......................................................................................................................15-6

get_instruction_readra() ..............................................................................................................15-7

get_instruction_readrb() ..............................................................................................................15-7

get_instruction_writerc() .............................................................................................................15-7

get_version() ..................................................................................................................................15-8
insert_result() ................................................................................................................................15-8
retrieve_instruction() ...................................................................................................................15-9
set_clock_enable_timeout() ........................................................................................................15-9
set_instruction_a() ......................................................................................................................15-10
set_instruction_b() .....................................................................................................................15-10
set_instruction_c() ......................................................................................................................15-10
set_instruction_timeout() ..........................................................................................................15-10
set_result_delay() ........................................................................................................................15-11
set_result_err_inject() ................................................................................................................15-11
set_result_value() ........................................................................................................................15-11
signal_fatal_error ........................................................................................................................15-11
signal_instructions_inconsistent ..............................................................................................15-12
signal_known_instruction_received ........................................................................................15-12
signal_result_done ......................................................................................................................15-12
signal_result_driven ...................................................................................................................15-13
signal_unknown_instruction_received ...................................................................................15-13

Avalon-ST Verilog HDL Testbench .................................................................16-1

Verifying Avalon-ST DUT ......................................................................................................................16-1
Understanding the Test Steps .................................................................................................................16-2

Setting up the Test ........................................................................................................................16-3

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Introduction to Avalon Verification IP SuiteUser Guide

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