Altera Avalon Verification IP Suite - Manual (Page 123)

set_transaction_idles()
set_transaction_idles(bit[31:0] idle_cycles)
Prototype:
Verilog HDL: idle_cycles
VHDL: idle_cycles , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the number of idle cycles to elapse before driving the out-going transaction. Description:
Verilog HDL, VHDL Language support:
set_transaction_eop()
set_transaction_eop(bit eop)
Prototype:
Verilog HDL: eop
VHDL:
eop
,
bfm_id
,
req_if(bfm_id)
Arguments:
void Returns:
Sets the status of the end of packet signal in the out-going transaction. Description:
Verilog HDL, VHDL Language support:
set_transaction_empty()
set_transaction_empty(STEmpty_t empty)
Prototype:
Verilog HDL:
empty
VHDL:
empty
,
bfm_id
,
req_if(bfm_id)
Arguments:
void Returns:
Sets the out-going transaction empty value. Description:
Verilog HDL, VHDL Language support:
set_transaction_error()
set_transaction_error(STError_t error)
Prototype:
Verilog HDL:
error
VHDL:
error
,
bfm_id
,
req_if(bfm_id)
Arguments:
void
Returns:
Sets the out-going transaction error value. Description:
Verilog HDL, VHDL Language support:
Altera Corporation Avalon-ST Source BFM
Send Feedback
8-11 set_transaction_idles()