Altera Avalon Verification IP Suite - Manual (Page 72)

signal_response_issued
signal_response_issued
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Notifies the testbench that a response has been driven out on the Avalon bus. Description:
Verilog HDL Language support:
Avalon-MM Slave BFM Altera Corporation
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