Altera Avalon Verification IP Suite - Manual (Page 53)

Figure 6-3: Avalon-MM Slave Receiving Write and Read Commands with No readdatavalid Signal
The following timing diagram illustrates the sequence of events for an Avalon-MM Slave BFM. The slave
BFM receives a write followed by a read when the
readdatavalid
signal is not present.
CLK
read
write
waitrequest
byteenable[3:0]
writedata[31:0]
readdata
D1
D2
S
cr_1
T
wt_1
T
wt_2
S
cr_2
T wr
transaction5 transaction6
S
rc_1,
S
atc
Table 6-2: Key to Annotations
The following table lists the annotations used in this figure.
Description Symbol
The initial command latency which is two cycles for transactions 1 and 2. T
i
The response wait time which is 3 cycles. The master gets this value using the get_response_
wait_time
command.
T
wt_1
The response wait time for the first read, which is 2 cycles. The slave sets this value using the
set_interface_wait_time
command.
T
wt_2
waitrequest
is sampled #1 after the falling edge of
clk
. T
wr
The response latency for the first read, which is 0 cycles. The master gets this time using the
get_response_latency
command.
T
rl_1
Signals write and read commands. The event name is
signal_command_issued
. S
cr_1,
S
cr_2
Signals the first read response. The event name is
signal_response_complete.
S
rc_1
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6-5 Timing