Altera Avalon Verification IP Suite - Manual (Page 202)

signal_instructions_inconsistent
signal_instructions_inconsistent
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that an instruction has changed while the previous instruction has not
completed. Description:
Verilog HDL Language support:
signal_known_instruction_received
signal_known_instruction_received
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals that a change has occured on the instruction interface and there is no
unknown value. Description:
Verilog HDL Language support:
signal_result_done
signal_result_done
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that a result has been received by the master. Description:
Verilog HDL Language support:
Nios II Custom Instruction Slave BFM Altera Corporation
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signal_instructions_inconsistent 15-12