Altera Avalon Verification IP Suite - Manual (Page 16)

2 Clock Source BFM
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The Avalon Verification IP Suite includes a Clock Source BFM that you can use to generate a clock signal
for your testbench.
The Clock Source BFM is only supported in Qsys. Note:
Parameters
Table 2-1: Clock Source BFM Parameter Settings
Description Legal Values Default Value Option
Specifies the clock rate in MHz. N/A 10 Clock rate
Clock Source API
clock_start()
clock_start
() Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Turns on the clock. Description:
Verilog HDL Language Support:
ISO
9001:2008
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