Altera Avalon Verification IP Suite - Manual (Page 184)

set_ci_clk_en()
void set_ci_clk_en() Prototype:
Verilog HDL:
bit enable
VHDL: bit enable , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the
ci_clk_en
signal synchronously with the clock. Description:
Verilog HDL, VHDL Language support:
set_clock_enable_timeout()
void set_clock_enable_timeout() Prototype:
Verilog HDL: int timeout
VHDL: int timeout , bfm_id , req_if
Arguments:
void
Returns:
Sets the timeout value for the clock enable. Sets the value to
0
(zero)to disable
timeouts.
Description:
Verilog HDL, VHDL Language support:
set_instruction_a()
void set_instruction_a()
Prototype:
Verilog HDL: ci_addr_t address
VHDL: ci_addr_t address , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the instruction register file address
a
value. Description:
Verilog HDL, VHDL Language support:
set_instruction_b()
void set_instruction_b()
Prototype:
Verilog HDL: ci_addr_t address
VHDL: ci_addr_t address , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the instruction register file address
b
value. Description:
Verilog HDL, VHDL Language support:
Altera Corporation Nios II Custom Instruction Master BFM
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14-9 set_ci_clk_en()