Altera Avalon Verification IP Suite - Manual (Page 126)

signal_src_transaction_complete
signal_src_transaction_complete
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that all pending transactions have completed. Description:
Verilog HDL Language support:
Avalon-ST Source BFM Altera Corporation
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