Altera Avalon Verification IP Suite - Manual (Page 153)

get_transaction_idles()
get_transaction_idles() Prototype:
Verilog HDL: None
VHDL: transaction_idles , bfm_id , req_if(bfm_id)
Arguments:
bit[31:0]
. Returns:
Returns the number of idle cycles in the most recently removed transaction. Description:
Verilog HDL, VHDL Language support:
get_transaction_queue_size()
get_transaction_queue_size() Prototype:
Verilog HDL: None
VHDL: transaction_queue_size , bfm_id , req_if(bfm_id)
Arguments:
int
. Returns:
Returns the length of the queue holding received transactions. Description:
Verilog HDL, VHDL Language support:
get_transaction_sop()
get_transaction_sop()
Prototype:
Verilog HDL: None
VHDL: transaction_sop , bfm_id , req_if(bfm_id)
Arguments:
bit
. Returns:
Returns the transaction start of packet status in the most recently removed
transaction. Description:
Verilog HDL, VHDL Language support:
get_version()
string get_version()
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
String
. Returns:
Returns BFM version as a string of three integers separated by periods. For
example, version 13.1 sp1 is encoded as "13.1.1". Description:
Verilog HDL Language support:
Altera Corporation Avalon-ST Monitor
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10-17 get_transaction_idles()