Altera Avalon Verification IP Suite - Manual (Page 175)

signal_api_call
signal_api_call
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Triggers when a client make an API call. Description:
Verilog HDL Language support:
write()
write()
Prototype:
VHDL:
bit[CDT_ADDRESS_W-1:0] address
logic[DATA_W-1:0] data
bfm_id
req_if(bfm_id)
Verilog HDL:
bit[CDT_ADDRESS_W-1:0] address
logic[DATA_W-1:0] data
Arguments:
void
Returns:
Overwrites the memory content at an address you specify. Description:
Verilog HDL, VHDL Language support:
External Memory BFM Altera Corporation
Send Feedback
signal_api_call 13-6