Altera Avalon Verification IP Suite - Manual (Page 149)

set_enable_c_single_packet_per_cycle()
set_enable_c_single_packet_per_cycle() Prototype:
Verilog HDL:
Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables a coverage point that ensures test coverage for number of transactions
that carry a single packet per cycle. It is disabled when packet transmission
is not supported. Description:
Verilog HDL Language support:
set_enable_c_transfer()
set_enable_c_transfer()
Prototype:
Verilog HDL:
Boolean
VHDL: N.A.
Arguments:
void Returns:
Enables a coverage point that ensures test coverage of a
valid
signal is
asserted correctly for different channels. It is disabled when the
ready
or
valid
signals are not supported.
Description:
Verilog HDL Language support:
set_enable_c_transaction_after_reset()
set_enable_c_transaction_after_reset() Prototype:
Verilog HDL:
Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables a coverage point that ensures test coverage for transaction on the
first cycle after reset. Description:
Verilog HDL Language support:
Altera Corporation Avalon-ST Monitor
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10-13 set_enable_c_single_packet_per_cycle()