Altera Avalon Verification IP Suite - Manual (Page 83)

set_enable_a_readid_sequence()
set_enable_a_readid_sequence()
Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables an assertion that verifies if the
readid
sequence follows the sequence
of the transactionid .
Description:
Verilog HDL Language support:
set_enable_a_read_response_sequence()
set_enable_a_read_response_sequence()
Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
void Returns:
Enables an assertion that ensures
readdatavalid
is asserted while read is
asserted for the same read transfer.
Description:
Verilog HDL Language support:
set_enable_a_read_response_timeout()
set_enable_a_read_response_timeout()
Prototype:
Verilog HDL:
Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables an assertion that ensures readdatavalid is asserted within
maximum allowed timeout period. Disabled when either
readdatavalid
is
not supported or the maximum allowed timeout period is less than 1.
Description:
Verilog HDL Language support:
Altera Corporation Avalon-MM Monitor
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7-11 set_enable_a_readid_sequence()