Altera Avalon Verification IP Suite - Manual (Page 187)

set_instruction_timeout()
void set_instruction_timeout() Prototype:
Verilog HDL:
int timeout
VHDL: int timeout , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the timeout value for an instruction. Sets the value to
0
(zero) to disable the
timeout.
Description:
Verilog HDL, VHDL Language support:
set_instruction_writerc()
void set_instruction_writerc()
Prototype:
Verilog HDL: logic enable
VHDL: logic enable , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the instruction register file write
c
value. Description:
Verilog HDL, VHDL Language support:
set_max_instruction_queue_size()
void set_max_instruction_queue_size(int size)
. Prototype:
Verilog HDL: int size
VHDL: int size , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the pending instruction queue size maximum threshold. Description:
Verilog HDL, VHDL Language support:
set_max_result_queue_size()
void set_max_result_queue_size(int size)
. Prototype:
Verilog HDL: int size
VHDL: int size , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the pending result queue size maximum threshold. Description:
Verilog HDL, VHDL Language support:
Nios II Custom Instruction Master BFM Altera Corporation
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set_instruction_timeout() 14-12