Altera Avalon Verification IP Suite - Manual (Page 210)

Figure 16-2: Timing from ModelSim Simulation
This figure shows the simulation timing from the ModelSim wave window.
clk
reset_bfm.reset
clk_bfm_clk_clk
reset_bfm_reset_reset
src_data[31:0]
src_channel[2:0]
src_valid
src_startofpacket
src_endofpacket
src_error[2:0]
src_empty[1:0]
src_ready
st_in_data[31:0]
st_in_valid
st_in_ready
st_in_startofpacket
st_in_endofpacket
st_in_empty[1:0]
st_in_error[2:0]
st_in_channel[2:0]
st_out_data[31:0]
st_out_valid
st_out_ready
st_out_startofpacket
st_out_endofpacket
st_out_empty[1:0]
st_out_error[2:0]
st_out_channel[2:0]
sink_data[31:0]
sink_channel[2:0]
sink_valid
sink_startofpacket
sink_endofpacket
sink_error[2:0]
sink_empty[1:0]
sink_ready
00000002 XXXXXXXX
0
0
0
00000002
0
0
0
00000001 00000003
0
0
0
00000001 00000003
0
0
0
‘bXXX
‘bXXX
‘bXX
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‘bXX
‘bXXX
‘bXXX
‘bXX
‘bXXX
‘bXXX
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‘bXXX
‘bXXX
‘bXX
Source BFM
DUT ( SC FIFO)
Sink BFM
Altera Corporation Avalon-ST Verilog HDL Testbench
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16-7 Observing the Results