Altera Avalon Verification IP Suite User Manual
Page 215
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Figure 17-3: Avalon-MM Master0 and Slave0 Writes
tb.clk
tb.reset
m0_waitrequest
m0_write
m0_read
m0_readdatavalid
m0_address[12:0]
m0_burstcount[3:0]
m0_writedata[31:0]
m0_byteenable[3:0]
m0_readdata[31:0]
s0_address[9:0]
s0_burstcount[3:0]
s0_writedata[31:0]
s0_byteenable[3:0]
s0_readdata[31:0]
s0_waitrequest
s0_write
s0_read
s0_readdatavalid
..
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Altera Corporation
Avalon-MM Verilog HDL and VHDL Testbenches
17-5
Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves
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