Altera Avalon Verification IP Suite - Manual (Page 112)

signal_write_response_complete
signal_write_response_complete Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Notifies the testbench that the write response has been received and inserted
into the response queue. Description:
Verilog HDL Language support:
Avalon-MM Monitor Altera Corporation
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