Altera Avalon Verification IP Suite - Manual (Page 20)

4 Avalon Interrupt Source and Interrupt Sink BFMs
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The Avalon Verification IP Suite includes Avalon Interrupt Source and Avalon Interrupt Sink BFMs for you
to generate interrupt signals in your testbench.
Parameters
Table 4-1: Clock Source BFM Parameter Settings
Description Legal Values Default Value Option
Interrupt Source
Specifies the polarity of the interrupt source signal.
Turn on this option to change the name of the
interrupt source signal port from
irq
to
irq_n
.
On/Off On Assert IRQ high
Specifies the width of the interrupt source signal. 1–32 1 IRQ width
Specifies whether the interrupt signal is asserted
or deasserted immediately after an API call or one
clock cycle after an API call. Turn on this option
to allow changes to the interrupt signal
immediately after an API call. Turn off this option
to allow changes to the interrupt signal on the
next clock edge. On/Off Off Asynchronous
IRQ
For VHDL BFMs only. Use this option to assign
a unique number to each BFM in the testbench
design. 1–1023 0 VHDL BFM ID
Interrupt Sink
Specifies the polarity of the interrupt sink signal.
Turn on this option to change the name of the
interrupt source signal port from
irq
to
irq_n
.
On/Off On Assert IRQ high
Specifies the width of the interrupt source signal. 1–32 1 IRQ width
ISO
9001:2008
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