Altera Avalon Verification IP Suite - Manual (Page 169)

signal_min_transaction_queue_size
signal_min_transaction_queue_size
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
None. Arguments:
void
Returns:
Triggers when the size of the pending queue falls below the minimum size. Description:
Verilog HDL Language support:
Tri-State Conduit BFM Altera Corporation
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signal_min_transaction_queue_size 12-10