Altera Avalon Verification IP Suite - Manual (Page 80)

set_enable_a_constant_during_clk_disabled()
set_enable_a_constant_during_clk_disabled()
Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables an assertion that ensures that all signals are held constant if
clken
is deasserted.
Description:
Verilog HDL Language support:
set_enable_a_constant_during_waitrequest()
set_enable_a_constant_during_waitrequest()
Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
void Returns:
Enables an assertion ensuring
read
,
write
,
writedata
,
address
,
burstcount, and byteenable are held constant if waitrequest is asserted.
Disabled when
waitrequest
is not supported.
Description:
Verilog HDL Language support:
set_enable_a_exclusive_read_write()
set_enable_a_exclusive_read_write() Prototype:
Verilog HDL:
Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables an assertion that ensures
read
and
write
are not asserted simulta-
neously. Disabled when either
read
or
write
is not supported.
Description:
Verilog HDL Language support:
Avalon-MM Monitor Altera Corporation
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set_enable_a_constant_during_clk_disabled() 7-8