Altera Avalon Verification IP Suite - Manual (Page 119)

get_response_queue_size()
get_response_queue_size()
Prototype:
Verilog HDL: None
VHDL: response_queue_size , bfm_id , req_if(bfm_id)
Arguments:
int
Returns:
Returns the number of transactions in the response queues. Description:
Verilog HDL, VHDL Language support:
get_src_ready()
get_src_ready()
Prototype:
Verilog HDL: None
VHDL:
src_ready
,
bfm_id
,
req_if(bfm_id)
Arguments:
bit Returns:
Returns the value of the source ready port. Description:
Verilog HDL, VHDL Language support:
get_src_transaction_complete()
get_src_transaction_complete()
Prototype:
Verilog HDL: None
VHDL:
src_transaction_complete
,
bfm_id
,
req_if(bfm_id)
Arguments:
bit Returns:
Returns the transaction complete status. Description:
Verilog HDL, VHDL Language support:
get_transaction_queue_size()
get_transaction_queue_size()
Prototype:
Verilog HDL: None
VHDL:
transaction_queue_size
,
bfm_id
,
req_if(bfm_id)
Arguments:
int
Returns:
Returns the number of transactions in the local queues. Description:
Verilog HDL, VHDL Language support:
Altera Corporation Avalon-ST Source BFM
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8-7 get_response_queue_size()