Altera Avalon Verification IP Suite - Manual (Page 70)

set_write_response_status()
void set_write_respose_status(AvalonWriteResponse_t status, int
index)
Prototype:
Verilog HDL: AvalonWriteResponse_t status , int index
VHDL: AvalonWriteResponse_t status , int index , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the write response status code. Description:
Verilog HDL, VHDL Language support:
signal_command_received()
signal_command_received
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Notifies the testbench that a command has been detected on an Avalon-MM port.
The testbench can respond with a
set_command_wait_time call on receiving this
event to dynamically back pressure the driving Avalon-MM master. Alternatively,
the previously set
wait_time might be used continuously for a set of transactions.
Description:
Verilog HDL Language support:
signal_error_exceed_max_pending_reads
signal_error_exceed_max_pending_reads
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Notifies the testbench of the error condition, in which the slave has more than
max_pending_reads pipelined read commands queued and waiting to be
processed.
Description:
Verilog HDL Language support:
Avalon-MM Slave BFM Altera Corporation
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