Altera Avalon Verification IP Suite - Manual (Page 111)

signal_response_complete
signal_response_complete Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Triggers when either
signal_read_response_complete
or
signal_write_
response_complete
is triggered. Indicates that either a read or a write
response was received and inserted into the response queue.
Description:
Verilog HDL Language support:
signal_transaction_fifo_overflow
signal_transaction_fifo_overflow
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Notifies the testbench that the FIFO is full and further transactions are
dropped. Description:
Verilog HDL Language support:
signal_transaction_fifo_threshold
signal_transaction_fifo_threshold
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Notifies the testbench that the transaction FIFO threshold level has exceeded. Description:
Verilog HDL Language support:
Altera Corporation Avalon-MM Monitor
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