Altera Avalon Verification IP Suite - Manual (Page 167)

set_valid_transaction_<role name>_out()
void set_valid_transaction_<role name>_out()
Prototype:
Verilog HDL: index , new_value
VHDL: index , new_value
Arguments:
void
Returns:
Sets the value of the valid transaction to the
<role name>_out
output port. Description:
Verilog HDL, VHDL Language support:
signal_all_transactions_complete
signal_all_transactions_complete
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Triggers when all the queued output and input transactions are completely
retrieved. Description:
Verilog HDL Language support:
signal_fatal_error
signal_fatal_error
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Notifies the testbench that a fatal error has occurred in this module. Description:
Verilog HDL Language support:
Tri-State Conduit BFM Altera Corporation
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set_valid_transaction_<role name>_out() 12-8