Features, Features -3 – Altera Integer Arithmetic IP User Manual
Page 104
The multipliers and adders of the ALTMULT_ADD megafunction are placed in the dedicated DSP block
circuitry of the Stratix devices. If all of the input data widths are 9-bits wide or smaller, the function uses
the 9 × 9-bit input multiplier configuration in the DSP block. If not, the DSP block uses 18 × 18-bit input
multipliers to process data with widths between 10 bits and 18 bits. If multiple ALTMULT_ADD
megafunctions occur in a design, the functions are distributed to as many different DSP blocks as possible
so that routing to these blocks is more flexible. Fewer multipliers per DSP block allow more routing
choices into the block by minimizing paths to the rest of the device.
The registers and extra pipeline registers for the following signals are also placed inside the DSP block:
• Data input
• Signed or unsigned select
• Add or subtract select
• Products of multipliers
In the case of the output result, the first register is placed in the DSP block. However the extra latency
registers are placed in logic elements outside the block. Peripheral to the DSP block, including data inputs
to the multiplier, control signal inputs, and outputs of the adder, use regular routing to communicate with
the rest of the device. All connections in the function use dedicated routing inside the DSP block. This
dedicated routing includes the shift register chains when you select the option to shift a multiplier's
registered input data from one multiplier to an adjacent multiplier.
For more information about implementing multipliers using DSP and memory blocks in Altera FPGAs,
.
Features
The ALTMULT_ADD megafunction offers the following features:
• Generates a multiplier to perform multiplication operations of two complex numbers
• Supports data widths of 1– 256 bits
• Supports signed and unsigned data representation format
• Supports pipelining with configurable output latency
• Provides a choice of implementation in dedicated DSP block circuitry or logic elements (LEs)
Note: When building multipliers larger than the natively supported size there may/will be a perform‐
ance impact resulting from the cascading of the DSP blocks.
• Provides an option to dynamically switch between signed and unsigned data support
• Provides an option to dynamically switch between add and subtract operation
• Provides an option to set up data shifting register chains
• Supports hardware saturation and rounding (for selected device families only)
• Supports optional asynchronous clear and clock enable input ports
• Supports systolic delay register mode (for Arria V, Cyclone V, and Stratix V devices only)
• Supports pre-adder with 8 pre-load coefficients per multiplier (for Arria V, Cyclone V, and Stratix V
devices only)
• Supports pre-load constant to complement accumulator feedback (for Arria V, Cyclone V, and Stratix
V devices only)
• In Arria V, Cyclone V, and Stratix V devices, the pre-adder, coefficient storage and systolic delay
register features are added to maximize flexibility. The following sections describe the new features.
UG-01063
2014.12.19
Features
9-3
ALTMULT_ADD (Multiply-Adder)
Altera Corporation