Altera Integer Arithmetic IP - Manual (Page 3)

ALTECC (Error Correction Code: Encoder/Decoder).......................................5-1
ALTECC_ENCODER Features..................................................................................................................5-2
Resource Utilization and Performance.....................................................................................................5-3
Verilog HDL Prototype (ALTECC_ENCODER)....................................................................................5-5
Verilog HDL Prototype (ALTECC_DECODER)....................................................................................5-5
VHDL Component Declaration (ALTECC_ENCODER)..................................................................... 5-6
VHDL Component Declaration (ALTECC_DECODER)..................................................................... 5-6
VHDL LIBRARY_USE Declaration..........................................................................................................5-7
Ports (ALTECC_ENCODER)....................................................................................................................5-7
Ports (ALTECC_DECODER).................................................................................................................... 5-7
Parameters (ALTECC_ENCODER)..........................................................................................................5-8
Parameters (ALTECC_DECODER)..........................................................................................................5-8
Design Example 1: ALTECC_ENCODER................................................................................................5-9
Understanding the Simulation Results......................................................................................... 5-9
Design Example 2: ALTECC_DECODER..............................................................................................5-12
Understanding the Simulation Results....................................................................................... 5-12
ALTERA_MULT_ADD (Multiply-Adder)......................................................... 6-1
Features......................................................................................................................................................... 6-2
Pre-adder...........................................................................................................................................6-3
Systolic Delay Register.....................................................................................................................6-6
Pre-load Constant............................................................................................................................ 6-9
Double Accumulator....................................................................................................................... 6-9
Verilog HDL Prototype.............................................................................................................................6-10
VHDL Component Declaration.............................................................................................................. 6-10
VHDL LIBRARY_USE Declaration........................................................................................................6-10
Ports.............................................................................................................................................................6-10
ALTERA_MULT_ADD Parameters.......................................................................................................6-12
Design Example: Implementing a Simple Finite Impulse Response (FIR) Filter............................. 6-19
Understanding the Simulation Results................................................................................................... 6-20
ALTMEMMULT (Memory-based Constant Coefficient Multiplier).................7-1
Features......................................................................................................................................................... 7-1
Resource Utilization and Performance.....................................................................................................7-2
Verilog HDL Prototype...............................................................................................................................7-2
VHDL Component Declaration................................................................................................................ 7-3
Ports...............................................................................................................................................................7-3
Parameters.....................................................................................................................................................7-4
Design Example: 8 × 8 Multiplier..............................................................................................................7-5
Understanding the Simulation Results..................................................................................................... 7-6
ALTMULT_ACCUM (Multiply-Accumulate)....................................................8-1
Features......................................................................................................................................................... 8-2
Resource Utilization and Performance.....................................................................................................8-2
Integer Arithmetic IP Cores User Guide TOC-3
Altera Corporation