Altera Integer Arithmetic IP - Manual (Page 149)

clk:in std_logic := '1';
ena:in std_logic := '1';
q:out std_logic_vector(Q_PORT_WIDTH-1 downto 0);
radical:in std_logic_vector(WIDTH-1 downto 0);
remainder:out std_logic_vector(R_PORT_WIDTH-1 downto 0));
end component;
VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
Ports
The following tables list the input and output ports for the ALTSQRT megafunction.
Table 11-1: ALTSQRT Megafunction Input Ports
Port Name Required Description
radical[]
Yes Data input port. The size of the input port depends on the
WIDTH
parameter value.
ena
No Active high clock enable input port.
clk
No Clock input port that provides pipelined operation for the
ALTSQRT
megafunction. For the values of
PIPELINE
parameter other than
0
(default value), the clock port must be connected.
aclr
No Asynchronous clear input port. that can be used at any time to reset the
pipeline to all
0
s, asynchronously to the clock signal.
Table 11-2: ALTSQRT Megafunction Output Ports
Port Name Required Description
remainder[]
Yes The square root of the radical. The size of the
remainder[]
port
depends on the
R_PORT_WIDTH
parameter value.
q[]
Yes Data output. The size of the
q[]
port depends on the
Q_PORT_WIDTH
parameter value.
Parameters
The following table lists the parameters for the ALTSQRT megafunction.
Parameter Name Type Required Description
WIDTH
Integer Yes Specifies the widths of the
radical[]
input port.
Q_PORT_WIDTH
Integer Yes Specifies the width of the
q[]
output port.
UG-01063
2014.12.19
VHDL LIBRARY_USE Declaration 11-3
ALTSQRT (Integer Square Root) Altera Corporation
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