Altera Integer Arithmetic IP - Manual (Page 110)

Figure 9-9: Systolic Delay Register Implementation of 4 Multipliers
a0
b0
Mult0
result
chainin
chainin
a1
b1
Mult1
a2
b2
Mult2
a3
b3
Mult3
result
+/-
+/-
+/-
+/-
Systolic registers
The sum of four multipliers is expressed in the following equation.
Figure 9-10: Sum of 4 Multipliers
UG-01063
2014.12.19
Systolic Delay Register 9-9
ALTMULT_ADD (Multiply-Adder) Altera Corporation
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