Altera Integer Arithmetic IP User Manual
Page 49
The following sequence corresponds with the numbered items in the figure:
• Data F0 is fed to the ECC encoder. As pipelining is enabled to have an output latency of 2 clock cycles,
the result of the encoding operation appears at the output port q[] 2 clock cycles later. The 8-bit input
data (F0) is encoded to generate a 13-bit output code word (14F0). The input data is appended with 5
parity bits. The ECC encoder encodes the data based on the Hamming Code scheme. The following
steps describe the Hamming Code algorithm and explain how the ECC encoder encodes input data F0
to generate the output code word of 14F0:
• In a 13-bit code word, there are 13 locations (bit positions), and each location holds 1 bit. There are
8 bits of original data, and the appended 5 parity bits. The locations (bit positions) for the bits must
be defined – bit positions that are powers of 2 are used as parity bits (positions 1, 2, 4, 8 …).
• The following table lists the bit positions, and the position of the parity bits of a 13-bit code word.
P5* is the extra parity bit added. The prefix P denotes parity.
Table 5-9: Design Example 1: Position of Parity Bits for a 13-Bit Code Word
Position
(1 )
(2 )
(3)
(4 )
(5 )
(6)
(7)
(8)
(9)
(10 )
(11)
(12 )
(13)
Parity Bits
P1
P2
—
P3
—
—
—
P4
—
—
—
—
P5*
• All other bit positions are for the data to be encoded. The least significant bit (LSB) of the data bit
fills the lowest bit position. In this case, starting from the LSB of the data, F0 (1111 0000 in binary)
fills the empty bit positions, starting from position (3), as shown in the following table. The prefixes
P and D denote parity and data, respectively. For the standard Hamming Code algorithm, the MSB
of the data bit fills the lowest bit position, unlike the Altera ECC megafunction, which fills up the
lowest bit position starting with the LSB. This bit order reduces the complexity of the circuit design.
Table 5-10: Design Example 1: Filling of Data Bits (1111 0000) for a 13-Bit Code Word
Position
(1 )
(2 )
(3)
(4 )
(5 )
(6)
(7)
(8)
(9)
(10 )
(11)
(12 )
(13)
Parity Bits
and Data
Bits
P1
P2
D1
0
P3
D2
0
D3
0
D4
0
P4
D5
1
D6
1
D7
1
D8
1
P5*
• Each parity bit calculates the parity for some of the bits in the code word. The position of the parity
bit determines the sequence of bits that it alternately checks and skips.
The following section list the sequence of bits that each parity bit checks:
Parity bit 1: check 1 bit, skip 1 bit, check 1 bit, skip 1 bit… (1, 3, 5, 7, 9, 11)
Parity bit 2: check 2 bits, skip 2 bits, check 2 bits, skip 2 bits… (2, 3, 6, 7, 10, 11)
Parity bit 4: check 4 bits, skip 4 bits, check 4 bits, skip 4 bits… (4, 5, 6, 7,1 2)
Parity bit 8: check 8 bits, skip 8 bits, check 8 bits, skip 8 bits… (8, 9, 10, 11, 12)
Table 5-11: Design Example 1: Calculation of Parity Bits
Position
(1 )
(2 )
(3)
(4 )
(5 )
(6)
(7)
(8)
(9)
(10 )
(11)
(12 )
(13)
Parity Bits
and Data
Bits
P1
P2
D1
0
P3
D2
0
D3
0
D4
0
P4
D5
1
D6
1
D7
1
D8
1
P5*
Calculate P1 0
0
—
0
0
—
1
—
1
—
—
Calculate P2 —
0
0
—
—
0
0
—
—
1
1
—
—
—
—
1
0
0
0
—
—
—
—
1
—
Calculate P4 —
—
—
—
—
—
—
0
1
1
1
1
—
Calculate P5 0
0
0
1
0
0
0
0
1
1
1
1
1
• Calculate the additional parity bits using an even parity checking on all the bits, including the
calculated parity bits. The additional parity bit P5* is calculated with an even parity checking on all
the bits from position (1) to position (12), as shown in the table.
• The generated code word is rearranged so that the data is at the LSB and the parity bits are at the
MSB. In this example, the generated code word is rearranged as shown in the following figure.
Figure 5-5: Design Example 1: Complete Generated Code Word after Rearrangement
P5*
MSB
LSB
1
P4
P3
P2
P1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
1
1
0
0
0
0
UG-01063
2014.12.19
Understanding the Simulation Results
5-11
ALTECC (Error Correction Code: Encoder/Decoder)
Altera Corporation