Altera Integer Arithmetic IP - Manual (Page 41)

Data Width Number of Parity Bits Total Bits (Code Word)
27-57 6+1 34-64
58-64 7+1 66-72
The parity bit derivation uses an even-parity checking. The additional 1 bit (shown in tthe table as +1) is
appended to the parity bits as the MSB of the code word. This ensures that the code word has an even
number of 1’s. For example, if the data width is 4 bits, 4 parity bits are appended to the data to become a
code word with a total of 8 bits. If 7 bits from the LSB of the 8-bit code word have an odd number of 1’s,
the 8th bit (MSB) of the code word is 1 making the total number of 1’s in the code word even.
The following figure shows the generated code word and the arrangement of the parity bits and data bits
in an 8-bit data input.
Figure 5-3: Parity Bits and Data Bits Arrangement in an 8-Bit Generated Code Word
4 parity bits 4 data bits
MSB LSB
8 1
The ALTECC_ENCODER megafunction accepts only input widths of 2 to 64 bits at one time. Input
widths of 12 bits, 29 bits, and 64 bits, which are ideally suited to Altera devices, generate outputs of 18 bits,
36 bits, and 72 bits respectively. The bit-selection limitation is controlled by the MegaWizard Plug-In
Manager.
Resource Utilization and Performance
The following tables provide resource utilization and performance information for the ALTECC
megafunction.
UG-01063
2014.12.19
Resource Utilization and Performance 5-3
ALTECC (Error Correction Code: Encoder/Decoder) Altera Corporation
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