Altera Integer Arithmetic IP - Manual (Page 5)

Design Example: 9-bit Square Root.........................................................................................................11-4
Understanding the Simulation Results................................................................................................... 11-4
PARALLEL_ADD (Parallel Adder).................................................................. 12-1
Feature.........................................................................................................................................................12-1
Resource Utilization and Performance...................................................................................................12-1
Verilog HDL Prototype.............................................................................................................................12-2
VHDL Component Declaration.............................................................................................................. 12-2
VHDL LIBRARY_USE Declaration........................................................................................................12-3
Ports.............................................................................................................................................................12-3
Parameters.................................................................................................................................................. 12-4
Design Example: Shift Accumulator....................................................................................................... 12-4
Understanding the Simulation Results................................................................................................... 12-5
Document Revision History..............................................................................13-1
Integer Arithmetic IP Cores User Guide TOC-5
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