Altera Integer Arithmetic IP - Manual (Page 109)

Figure 9-8: Systolic Delay Register Implementation of 2 Multipliers
a0
b0
Mult0
result
chainin
a1
b1
Mult1
+/-
+/-
Systolic registers
The sum of two multipliers is expressed in the following equation.
The following figure shows the systolic delay register implementation of 4 multipliers.
9-8 Systolic Delay Register
UG-01063
2014.12.19
Altera Corporation ALTMULT_ADD (Multiply-Adder)
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